EL2142C january 1996 rev a EL2142C differential line receiver note: all information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ``controlled document''. current revisions, if any, to these specifications are maintained at the factory and are available upon your request. we recommend checking the revision level before finalization of your design documentation. ? 1996 elantec, inc. features # differential input range g 2.3v # 150 mhz 3 db bandwidth # 400 v/ m s slewrate # g 5v supplies or single supply # 50 ma minimum output current # output swing (100 x load) to within 1.5v of supplies # low power b 11 ma typical applications # twisted pair receiver # differential line receiver # vga over twisted pair # adsl/hdsl receiver # differential to single ended amplification. # reception of analog signals in a noisy environment. ordering information part no. temp. range package outline y EL2142Cn b 40 cto a 85 c 8-pin dip mdp0031 EL2142Cs b 40 cto a 85 c 8-pin soic mdp0027 general description the EL2142C is a very high bandwidth amplifier designed to extract the difference signal from noisy environments, and is thus primarily targeted for applications such as receiving sig- nals from twisted pair lines, or any application where common mode noise injection is likely to occur. the EL2142C is stable for a gain of one, and requires two exter- nal resistors to set the voltage gain. the output common mode level is set by the reference pin (v ref ), which has a b 3 db bandwidth of over 100 mhz. gen- erally, this pin is grounded, but it can be tied to any voltage reference. the output can deliver a minimum of g 50 ma and is short circuit protected to withstand a temporary overload condition. connection diagrams EL2142C so, p-dip 2142-1
EL2142C differential line receiver absolute maximum ratings (t a e 25 c) supply voltage (v cc v ee ) 0v to 12.6v maximum output current g 60 ma storage temperature range b 65 cto a 150 c operating junction temperature a 150 c lead temperature ( k 5 sec) a 300 c recommended operating temperature b 40 cto a 85 c important note: all parameters having min/max specifications are guaranteed. the test level column indicates the specific device testing actually performed during production and quality inspection. elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the ltx77 series system. unless otherwise noted, all tests are pulsed tests, therefore t j e t c e t a . test level test procedure i 100% production tested and qa sample tested per qa test plan qcx0002. ii 100% production tested at t a e 25 c and qa sample tested at t a e 25 c, t max and t min per qa test plan qcx0002. iii qa sample tested per qa test plan qcx0002. iv parameter is guaranteed (but not tested) by design and characterization data. v parameter is typical value at t a e 25 c for information purposes only. dc electrical characteristics (v cc ea 5v, v ee eb 5v, t a e 25c, v in e 0v, r l e 100, unless otherwise specified) parameter description min typ max test units level v supply supply operating range (v cc v ee ) g 3.0 g 5.0 g 6.3 i v i s power supply current (no load) 11 14 i ma v os input referred offset voltage b 25 10 40 i mv i in input bias current (v in ,v inb ,v ref ) b 20 6 20 i m a z in differential input resistance 400 v k x c in differential input capacitance 1 v pf v diff differential input range g 2.0 g 2.3 i v a vol open loop voltage gain 75 v db v in input common mode voltage range b 2.6 a 4.0 i v v out output voltage swing (50 x load to gnd) g 2.9 g 3.1 i v i out (min) minimum output current 50 60 i ma v n input referred voltage noise 36 v nv/ s hz v ref output voltage control range b 2.5 a 3.3 i v psrr power supply rejection ratio 60 70 i db cmrr2 input common mode rejection ratio (v in e g 2v) 60 70 i db cmrr1 input common mode rejection ratio (full v in range) 50 60 i db 2 td is 3.3in
EL2142C differential line receiver ac electrical characteristics (v cc ea 5v, v ee eb 5v, t a e 25c, v in e 0v, r load e 100, unless otherwise specified) parameter description min typ max test units level bw( b 3db) b 3 db bandwidth (gain e 1) 150 v mhz sr slewrate 400 v v/ m s t stl settling time to 1% 15 v ns gbwp gain bandwidth product 200 v mhz v ref bw( b 3 db) v ref b 3db bandwidth 130 v mhz v ref sr v ref slewrate 100 v v/ m sec dg differential gain at 3.58 mhz. 0.2 v % d i differential phase at 3.58 mhz. 0.2 v pin description pin number pin name function 1v fb feedback input 2v in non-inverting input 3v inb inverting input 4v ref sets output voltage level to v ref when v in e v inb 5nc 6v cc positive supply voltage 7v ee negative supply voltage 8v out output voltage 3 td is 1.8in
EL2142C differential line receiver typical performance curves i s vs supply voltage 2142 2 (gain e 1) frequency response 2142 3 vs resistor r1 (gain e 4) frequency response 2142 4 cmrr vs frequency 2142 5 v ref frequency response 2142 6 v in e 2v pk/pk (gain e 3, r load e 100 x ) distortion vs frequency 2142 7 4
EL2142C differential line receiver applications information 2142-8 gain equation v out e ((r2 a r1)/r1) c (v in -v inb a v ref ) when r1 tied to gnd v out e ((r2 a r1)/r1) c (v in -v inb ) when r1 tied to v ref choice of feedback resistor for a gain of one, v out may be shorted back to v fb , but 100 x 200 x improves the bandwidth. for gains greater than one, there is little to be gained from choosing resistor r1 value below 200 x , for it would only result in increased power dissipation and potential signal distortion. above 200 x , the bandwidth response will develop some peaking (for a gain of one), but substantially higher r1 values may be used for higher voltage gains, such as up to 1 k x at a gain of four before peaking will develop. capacitance considerations as with many high bandwidth amplifiers, the EL2142C prefers not to drive highly capacitive loads. it is best if the capacitance on v out is kept below 10 pf if the user does not want gain peaking to develop. the v fb node forms a poten- tial pole in the feedback loop, so capacitance should be minimized on this node for maximum bandwidth. the amount of capacitance tolerated on any of these nodes in an actual application will also be dependent on the gain setting and the resistor values in the feedback network. 5
EL2142C differential line receiver typical applications 2142-9 figure 1. typical twisted pair application 2142-10 figure 2. coaxial cable driver 6
EL2142C differential line receiver typical applications e contd. 2142-11 figure 3. single supply receiver 2142-12 2142-13 figure 4. compensated line receiver 7
EL2142C january 1996 rev a EL2142C differential line receiver 2142-14 figure 5. two channel multiplexer general disclaimer specifications contained in this data sheet are in effect as of the publication date shown. elantec, inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. elantec, inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. elantec, inc. 1996 tarob court milpitas, ca 95035 telephone: (408) 945-1323 (800) 333-6314 fax: (408) 945-9305 european office: 44-71-482-4596 warning e life support policy elantec, inc. products are not authorized for and should not be used within life support systems without the specific written consent of elantec, inc. life support systems are equipment in- tended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. users contemplating application of elantec, inc. products in life support systems are requested to contact elantec, inc. factory headquarters to establish suitable terms & conditions for these applications. elantec, inc.'s warranty is limited to replace- ment of defective components and does not cover injury to per- sons or property or other consequential damages. printed in u.s.a. 8
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